This invention relates generally to digital circuits for regenerating a jittered clock signal. More particularly, this invention relates to a dejitter circuit which receives a jittered telecommunications signal, and which uses a clock source of higher frequency for regenerating the telecommunications signal at the rate of the incoming telecommunications signal.
DS0, DS1, DS2, and DS3 telecommunications signals are well defined according to CCITT specifications. Essentially, a DS0 signal is a signal having a bit rate of 64 Kbits/sec. A DS1 signal is composed of twenty-four DS0 segments plus overhead for a total bit rate of 1.544 Mbits/sec (plus or minus approximately 200 b/sec). In turn, four DS1 signals plus some overhead (bit stuffing) constitute a 6.312 Mb/sec DS2 signal, and four DS2 signals plus some additional overhead constitutes a 44.736 Mb/sec DS3 signal.
DS3 signals are commonly used between central offices for high speed communication. When the DS3 signal is received, it is often demultiplexed into its seven composite DS2 signals, with the bit stuffing utilized for control and essentially removed from the DS2 signals. In turn, the DS2 signals are often demultiplexed into their four composite DS1 signals with the DS2 bit stuffing utilized for control and essentially removed from the resulting DS1 signals. Each resulting DS1 signal has a bit rate of approximately 1.544 Mb/sec plus or minus 200 b/sec. However, because in generating the DS1 signal the overhead or stuffing bits are removed, the bit stream of the DS1 signal is gapped or "jittered". Additional jitter termed "transport" or "systematic" jitter is also found in the DS1 signal due to the fact that all systems introduce noise into the signals which they are carrying. Jitter is undesirable as it can introduce error in the decoding of the signal.
With the advent of the optical network, additional telecommunication signals have been defined according to CCITT specifications. The basic SONET signal is an STS-1 signal having a bit rate of 51.84 Mb/sec. An STS-3 signal (155.52 Mb/sec) has three times the bit rate of the STS-1 signal. Often the STS-1 or STS-3 signals are used to carry the data payloads of DS0, DS1, DS2 and DS3 signals. In fact, the STS signals can also be required to carry the data payload of standard European signals such as a 2.048 Mb/sec signal.
Standard devices such as phase locked loops are known in the art for tracking signal rates and for generating a clock of the nominal received rate for eliminating jitter. Phase locked loops however, have several drawbacks including expense and the requirement of analog implementation. The subject invention eliminates the need for an analog phase locked loop through the use of a small amount of digital circuitry capable of implementation on a small section of an LSI circuit.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a digital circuit for regenerating a clock signal for a jittered telecommunications signal at the nominal rate of the jittered telecommunications signal.
It is another object of the invention to provide a digital dejitter circuit where the rate of the generated output signal is finely tuned to the rate of the incoming signal and has minimal jitter.
It is a further object of the invention to provide a digital phase lock loop circuit which follows a nominally 2.048 MHz gapped telecommunications signal and generates a nominally 2.048 MHz ungapped clock signal from a 58.32 MHz signal.
In accord with the objects of the invention, the digital clock dejitter circuit broadly comprises a FIFO means for receiving the incoming gapped signal, a digital, fractional FIFO fullness gauge means for tracking the average input and output rates to and from the FIFO means and for generating therefrom a control indication, and a controllable digital frequency generator means for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal.
The FIFO means is preferably implemented with a RAM. The digital, fractional FIFO fullness gauge means is preferably implemented with a write counter which tracks the writing of bytes into the RAM, a read counter which tracks the reading of bytes out of the RAM, a comparator (subtraction) means for taking the difference of the write and read counters to obtain the FIFO length or depth, and a fast clock divider means (which is part of the controllable digital frequency generator means) for providing a digital indication regarding how close the system is to the reading of another byte from the FIFO. Effectively, the comparator provides the FIFO gauge means with a digital integer value of the bytes in the FIFO, while the fast clock counter means provides the FIFO gauge means with a fractional value. The FIFO fullness indication is a control indication which is used to slightly change the nominal frequency generated by the controllable digital frequency generator means. The control indication is a digital signal which is either processed to represent the desired output frequency of the system, or is processed to represent a change in output frequency of the system. In any event, the processed control indication is fed to the controllable digital frequency generator means.
The controllable digital frequency generator means is preferably implemented with an adder, a register, and the fast clock divider. The adder has at least two inputs and two outputs. The outputs include a carry output which is fed to the fast clock divider, and a sum (remainder) output which is fed to the register. The two inputs include the remainder which is provided to the adder by the register, and the processed control indication from the FIFO gauge means. Similarly, the fast clock divider has two inputs and two outputs. The two inputs are the fast clock, and the carry output of the adder. The fast clock divider receives the fast clock and counts in order to conduct a divide by value x--or divide by value x+1. The carry output of the adder is used to determine whether the fast clock divider divides by x or by x+1. The outputs of the counter are a read signal which causes a byte to be read out from the FIFO at the end of a count cycle, and a fast clock count which is used as the fractional value by the FIFO gauge means.
By arranging the inputs (other than the remainder) to the adder to normally (i.e., in steady state) sum to a value equal to the ratio of the number of times a divide by x is required to the sum of the number of times a divide by x plus the number of times a divide by x+1 is required, and by causing a divide by x if the carry value is zero and a divide by x+1 if the carry value is one, the carry output will cause the fast clock divider to output the nominally desired frequency. When the FIFO fills or depletes, the control signal from the FIFO fullness gauge means changes. Thus, one input to the adder is changed. Depending on the direction of the change, additional or fewer carries will result over a period of time, and the output frequency generated by the fast clock divider will change accordingly.
To dejitter a jittered European telecommunications 2.048 Mb/sec signal by using a faster STS-3 input clock signal, a divide by twenty-eight--divide by twenty-nine circuit which receives a 58.32 MHz clock signal (which is three/eighths the rate of a 155.52 Mb/sec STS-3 clock signal) is utilized. To generate exactly a 2.048 Mb/sec signal from the 58.32 MHz signal, a divide by 28.4765625 of the fast clock is required. Thus the divide by twenty-nine should occur exactly 47.65625% of the time and the divide by twenty-eight should occur exactly 52.34375% of the time. In order to guarantee such an arrangement, 0.4765625 (in digital form=0.0111 1010 0000 0000 0) is added to the adder each cycle. Whenever the carry out is one (which would be 47.65625% of the time), the next divide cycle is divide by twenty-nine. Whenever the carry out is zero (i.e., 52.34375% of the time), the next divide cycle is divide by twenty-eight.
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided drawings.